The present invention relates to a semiconductor device having memory cells, a method of testing the semiconductor device, and an electronic instrument.
In semiconductor device fabrication, it is general to conduct various tests at the wafer level whenever possible in order to avoid wasting processes such as packaging as much as possible.
For the inspection of semiconductor devices at the wafer level, tests are conducted in which the semiconductor devices are connected to a tester (semiconductor device test system) through a probe card equipped with a plurality of probes. As shown in FIG. 14 by a pattern diagram, for example, in this inspection, separate probes 3010 of a probe card 3000 are brought into contact with terminals such as data input/output terminals, which are formed on each of chips of a semiconductor wafer 2000, and the input and output of address signals, data signals, control signals and power sources are conducted between the tester and the semiconductor devices. Such the tester has a lot of input/output circuits for inputting and outputting data with the semiconductor devices and drivers for sending address signals and control signals, but the numbers of such input/output circuits and drivers are limited of themselves.
The number of semiconductor devices mounted on a single wafer, that is, the number of chips and the number of terminals disposed in the separate chips have been increasing more and more with the realization of large scale integration. Accordingly, to inspect many semiconductor devices formed on a single wafer, tests need to be divided and conducted for many times, requiring long hours for inspection.
In addition, it is known that in order to inspect semiconductor devices at the wafer level, contacting the probes 3010 to separate terminals of the semiconductor devices, such as address input terminals, causes damage in the terminals and problems occur in bonding of the terminals due to such the damage in the terminals, leading to the semiconductor device as a completed product to be defective. Therefore, the number of times to contact the probes to the terminals is preferably as small as possible.
Furthermore, in the semiconductor devices, burn-in is often conducted to cause as many initial failures as possible before shipping and to take defective products away from the products to be shipped. Moreover, burn-in is the test that electronic devices are operated at temperatures and voltages higher than normal operating conditions and strong stress is applied to the electronic devices, whereby initial failures are generated for a short time to eliminate defective devices before shipping. Traditionally, burn-in in the semiconductor devices has often been conducted for completed products after packaging with ceramics and resins. However, the manner wastes the assembly cost of chips found defective in burn-in. Considering this, the wafer burn-in which is done at the wafer level becomes to be conducted.
In the wafer burn-in, a semiconductor wafer is placed in a burn-in system for exclusive use in order to operate chips at higher temperature conditions. In the meantime, such the burn-in system has been provided with tester functions recently. However, the number of semiconductor devices to be tested simultaneously by such a tester equipped in the burn-in system is often fewer than that of a typical tester. Accordingly, testing all the semiconductor devices on a wafer takes much longer time than the typical tester does.